Embedded, Hardware, Programming

Introduction to Clash for FPGA Development – Index

I work a lot with FPGAs, and I have been interested in any language that makes it easier to develop hardware for them. Since I am currently a PhD student at the CAES group of the Unversity of Twente, I have been interested in learning Clash or CAES Language for Synthesizable Hardware, a functional hardware description language built upon Haskell. Because I am not an expert in functional programming and Haskell, I have had to ask people who are working on/with Clash about things I am not familiar with. Now I want to share my bit of knowledge and experience about Clash by writing about it.

Reminder: These posts are currently written for Clash 0.7.2, but the newest version is Clash 0.99.1. I will try to update the post soon(-ish), but if you want to see how to change the code, you can follow the migration guide.

This is the index of all the posts about Clash on this blog. It is still a work in progress, and will be updates as now posts are written.

  1. Part 1 – Basic introduction to combinatorial logic
  2. Part 2 – Bug fixes, much cleaner code, simulation, synchronous logic, and test benches

All the code written in the posts are up on Github. For questions/constructive criticism you can find me on Twitter @BitlogIT

Additional posts:

About the author / 

Oguz Meteer // guztech

Oguz Meteer (guztech) is an embedded systems engineer, and a PhD student at the University of Twente. His interests lie in computer graphics, FPGA development, and formal verification of hardware. He is also a consultant at GuzTech.

Who are we?

We are a collective of people with different backgrounds and a shared interest in the outskirts of technology.

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